Display apparatus comprising thin film transistor

ABSTRACT

A display apparatus comprises a first signal line on a substrate, a second signal line intersecting with the first signal line, a first gate electrode, a first source electrode, a first drain electrode, and a second gate electrode disposed on the same layer as that of the first signal line, a first active layer spaced apart from the first gate electrode and partially overlapped with the first gate electrode, a second active layer spaced apart from the second gate electrode and partially overlapped with the second gate electrode, and a first electrode of a display device connected with the second active layer.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.17/122,915, filed on Dec. 15, 2020, which claims the benefit of theKorean Patent Application No. 10-2019-0167721 filed on Dec. 16, 2019,which are hereby incorporated by reference in their entirety for allpurposes as if fully set forth herein.

BACKGROUND Field of the Disclosure

The present disclosure relates to a display apparatus and a method formanufacturing the same. In more detail, the present disclosure relatesto a display apparatus capable of simplifying a structure and amanufacturing process, and a method for manufacturing the same.

Description of the Background

A display apparatus which displays various information on a screen is atechnology-intensive device in which core technologies of an informationcommunication field are integrated. Recently, the display apparatus hasbeen developed so as to realize thin profile, lightness, portability,and furthermore, high performance. Typical examples of the displayapparatus may be a liquid crystal display (LCD) device and an organiclight emitting diode display (OLED) device.

Generally, a mask process using a photo mask is carried out severaltimes so as to manufacture the display apparatus. Each mask processrequires cleaning, exposure, developing and etching steps, or the like.Accordingly, whenever one mask process is added, it may cause theincrease of manufacturing time and cost, and furthermore, it may causethe increase of possibility of defect and defect rate. As a result, amanufacturing yield is lowered. Thus, in order to lower a manufacturingcost, and to improve a production yield and efficiency, it is necessaryto simplify a structure and a manufacturing process.

SUMMARY

Accordingly, the present disclosure has been made in view of the aboveproblems, and to provide a display apparatus capable of simplifying astructure and a manufacturing process, and a method for manufacturingthe same.

The present disclosure is also to provide a thin film transistor with asimplified structure and manufacturing process, and a display apparatuscomprising the thin film transistor, in which the thin film transistorhas a bottom gate structure using an oxide semiconductor material, andthus it is possible to omit a light shielding layer and a process offorming source and drain electrodes.

Further, the present disclosure is to provide a method for manufacturinga display apparatus comprising a thin film transistor with a simplifiedstructure and manufacturing process.

In accordance with an aspect of the present disclosure, the above andother features can be accomplished by the provision of a displayapparatus comprising a first signal line on a substrate, a second signalline intersecting with the first signal line, a first gate electrode, afirst source electrode, a first drain electrode, and a second gateelectrode disposed on the same layer as that of the first signal line, afirst active layer spaced apart from the first gate electrode andpartially overlapped with the first gate electrode, a second activelayer spaced apart from the second gate electrode and partiallyoverlapped with the second gate electrode, and a first electrode of adisplay device connected with the second active layer, wherein thesecond signal line includes a first portion and a second portiondisposed on the same layer as that of the first signal line, and spacedapart from each other with the first signal line therebetween, and afirst connection electrode configured to connect the first portion andthe second portion with each other, the first gate electrode isconnected with any one of the first signal line and the second signalline, any one of the first source electrode and the first drainelectrode is connected with the second gate electrode, and the other ofthe first source electrode and the first drain electrode is connectedwith the other of the first signal line and the second signal line.

Any one of the first signal line and the second signal line is a gateline, and the other is a data line.

Any one of the first source electrode and the first drain electrode isformed as one body with the second gate electrode.

A gate insulating film is disposed on the first gate electrode, thefirst source electrode, the first drain electrode, and the second gateelectrode, and the first active layer is disposed on the gate insulatingfilm, and the first active layer contacts the first source electrode andthe first drain electrode via contact holes formed in the gateinsulating film.

The first active layer includes a channel region, and a source regionand a drain region connected with the channel region, wherein the sourceregion contacts the first source electrode, and the drain regioncontacts the first drain electrode.

The source region and the drain region are formed by a process ofproviding conductivity to an oxide semiconductor layer.

The first connection electrode and the first electrode of the displaydevice are manufactured at the same time by the same mask process.

The first connection electrode includes a transparent conductive oxidelayer formed of the same material as that of the first electrode of thedisplay device, and a metal layer on the transparent conductive oxidelayer.

The first gate electrode is disposed between the substrate and the firstactive layer, and the second gate electrode is disposed between thesubstrate and the second active layer.

Each of the first active layer and the second active layer includes anoxide semiconductor material.

The first active layer includes a first oxide semiconductor layer on thefirst gate electrode, and a second oxide semiconductor layer on thefirst oxide semiconductor layer.

The second active layer includes a first oxide semiconductor layer onthe second gate electrode, and a second oxide semiconductor layer on thefirst oxide semiconductor layer.

The display apparatus further comprises a first capacitor electrodedisposed on the same layer as that of the second gate electrode.

The first capacitor electrode is formed as one body with the second gateelectrode.

The first capacitor electrode is overlapped with the first electrode ofthe display device, to thereby form a first capacitor.

The display apparatus further comprises a second capacitor electrode, asecond source electrode and a second drain electrode, wherein the secondcapacitor electrode is connected with any one of the second sourceelectrode and the second drain electrode.

The second capacitor electrode is formed as one body with the secondactive layer.

The display apparatus further comprises a third signal line whichintersects with any one of the first signal line and the second signalline.

The third signal line is a driving power line.

In accordance with another aspect of the present disclosure, there isprovided a method for manufacturing a display apparatus comprisingproviding a first signal line, a first gate electrode, a first sourceelectrode, a first drain electrode, a second gate electrode, and a firstportion and a second portion of a second signal line on a substrate,providing a gate insulating film on the first signal line, the firstgate electrode, the first source electrode, the first drain electrode,the second gate electrode, and the first portion and the second portionof the second signal line, providing a first active layer and a secondactive layer on the gate insulating film, wherein at least a portion ofthe first active layer is overlapped with the first gate electrode, andat least a portion of the second active layer is overlapped with thesecond gate electrode, selectively providing conductivity to the firstactive layer and the second active layer to make conducting regions inthe first active layer and the second active layer, providing aprotection layer on the first active layer and the second active layer,and providing a first connection electrode and a first electrode of adisplay device on the protection layer, wherein the first connectionelectrode connects the first portion of the second signal line with thesecond portion of the second signal line, the first gate electrode isconnected with any one of the first signal line and the second signalline, any one of the first source electrode and the first drainelectrode is connected with the second gate electrode, and the other ofthe first source electrode and the first drain electrode is connectedwith the other of the first signal line and the second signal line.

The process of selectively providing conductivity to the first activelayer and the second active layer includes a doping process usingdopant.

The process of providing the first connection electrode and the firstelectrode of the display device includes providing a transparentconductive oxide (TCO) layer on the protection layer, providing a metallayer on the transparent conductive oxide layer, and patterning thetransparent conductive oxide layer and the metal layer, wherein themetal layer is removed from the area for the first electrode of thedisplay device.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and other advantages of the presentdisclosure will be more clearly understood from the following detaileddescription taken in conjunction with the accompanying drawings.

In the drawings:

FIG. 1 is a schematic view illustrating a display apparatus according toone aspect of the present disclosure;

FIG. 2 is a circuit diagram for any one pixel of FIG. 1 ;

FIG. 3 is a plan view illustrating the pixel of FIG. 2 ;

FIG. 4 is a cross sectional view along of FIG. 3 ;

FIG. 5 is a cross sectional view illustrating a pixel of a displayapparatus according to another aspect of the present disclosure;

FIG. 6 is a cross sectional view illustrating a pixel of a displayapparatus according to another aspect of the present disclosure;

FIG. 7 is a plan view illustrating a pixel of a display apparatusaccording to another aspect of the present disclosure;

FIG. 8 is a cross sectional view along II-II′ of FIG. 7 ;

FIG. 9 is a plan view illustrating pixels of a display apparatusaccording to another aspect of the present disclosure;

FIG. 10 is a circuit diagram for any one pixel of a display apparatusaccording to another aspect of the present disclosure;

FIG. 11 is a circuit diagram for any one pixel of a display apparatusaccording to another aspect of the present disclosure;

FIGS. 12A and 12B are respectively a plan view and a cross sectionalview for a manufacturing process of the display apparatus according toone aspect of the present disclosure;

FIGS. 13A and 13B are respectively a plan view and a cross sectionalview for a manufacturing process of the display apparatus according toone aspect of the present disclosure;

FIGS. 14A, 14B, 14C, 14D and 14E are respectively a plan view and crosssectional views for a manufacturing process of the display apparatusaccording to one aspect of the present disclosure;

FIGS. 15A and 15B are respectively a plan view and a cross sectionalview for a manufacturing process of the display apparatus according toone aspect of the present disclosure; and

FIGS. 16A, 16B, 16C, 16D and 16E are respectively a plan view and crosssectional views for a manufacturing process of the display apparatusaccording to one aspect of the present disclosure.

DETAILED DESCRIPTION

Advantages and features of the present disclosure, and implementationmethods thereof will be clarified through the following aspects,described with reference to the accompanying drawings. The presentdisclosure may, however, be embodied in different forms and should notbe construed as being limited to the aspects set forth herein. Rather,these aspects are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the present disclosure tothose skilled in the art. Further, the present disclosure is onlydefined by the scope of the claims.

The shapes, sizes, ratios, angles, and numbers disclosed in the drawingsfor describing aspects of the present disclosure are merely examples,and thus the present disclosure is not limited to the illustrateddetails. Like reference numerals refer to like elements throughout. Inthe following description, when the detailed description of the relevantknown function or configuration is determined to unnecessarily obscurethe important point of the present disclosure, the detailed descriptionwill be omitted.

In the case in which “comprise,” “have,” and “include” described in thepresent specification are used, another part may also be present unless“only” is used. The terms in a singular form may include plural formsunless noted to the contrary.

In construing an element, the element is construed as including an errorregion although there is no explicit description thereof.

In describing a positional relationship, for example, when thepositional order is described as “on,” “above,” “below,” “beneath”, and“next,” the case of no contact therebetween may be included, unless“just” or “direct” is used.

If it is mentioned that a first element is positioned “on” a secondelement, it does not mean that the first element is essentiallypositioned above the second element in the figure. The upper part andthe lower part of an object concerned may be changed depending on theorientation of the object. Consequently, the case in which a firstelement is positioned “on” a second element includes the case in whichthe first element is positioned “below” the second element as well asthe case in which the first element is positioned “above” the secondelement in the figure or in an actual configuration.

In describing a temporal relationship, for example, when the temporalorder is described as “after,” “subsequent,” “next,” and “before,” acase which is not continuous may be included, unless “just” or “direct”is used.

It will be understood that, although the terms “first,” “second,” etc.may be used herein to describe various elements, these elements shouldnot be limited by these terms. These terms are only used to distinguishone element from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the present disclosure.

It should be understood that the term “at least one” includes allcombinations related with any one item. For example, “at least one amonga first element, a second element and a third element” may include allcombinations of two or more elements selected from the first, second andthird elements as well as each element of the first, second and thirdelements.

Features of various aspects of the present disclosure may be partiallyor overall coupled to or combined with each other, and may be variouslyinter-operated with each other and driven technically as those skilledin the art can sufficiently understand. The aspects of the presentdisclosure may be carried out independently from each other, or may becarried out together in a co-dependent relationship.

In the drawings, the same or similar elements are denoted by the samereference numerals even though they are depicted in different drawings.

In the aspects of the present disclosure, a source electrode and a drainelectrode are distinguished from each other, for convenience ofexplanation. However, the source electrode and the drain electrode areused interchangeably. Thus, the source electrode may be the drainelectrode, and the drain electrode may be the source electrode. Also,the source electrode in any one aspect of the present disclosure may bethe drain electrode in another aspect of the present disclosure, and thedrain electrode in any one aspect of the present disclosure may be thesource electrode in another aspect of the present disclosure.

In one or more aspects of the present disclosure, for convenience ofexplanation, a source region is distinguished from a source electrode,and a drain region is distinguished from a drain electrode. However,aspects of the present disclosure are not limited to this structure. Forexample, a source region may be a source electrode, and a drain regionmay be a drain electrode. Also, a source region may be a drainelectrode, and a drain region may be a source electrode.

FIG. 1 is a schematic view illustrating a display apparatus 100according to one aspect of the present disclosure.

As shown in FIG. 1 , the display apparatus 100 according to one aspectof the present disclosure includes a display panel 110, a gate driver120, a data driver 130, and a controller 140.

The display panel 110 includes gate lines (GL) and data lines (DL), anda pixel (P) which is arranged at a crossing portion of the gate line(GL) and the data line (DL). The pixel (P) includes a display device710, and a pixel driver (PDC) configured to drive the display device710. An image is displayed on the display panel 110 by driving the pixel(P).

The controller 140 controls the gate driver 120 and the data driver 130.

The controller 140 outputs a gate control signal (GCS) for controllingthe gate driver 120, and a data control signal (DCS) for controlling thedata driver 130 by the use of vertically/horizontally synchronizedsignal and clock signal supplied from an external system (not shown).Also, the controller 140 samples input video data, which is providedfrom the external system, and then re-aligns the sampled video data, andsupplies the re-aligned digital video data (RGB) to the data driver 130.

The gate control signal (GCS) includes a gate start pulse (GSP), a gateshift clock (GSC), a gate output enable signal (GOE), a start signal(Vst), and a gate clock (GCLK). Also, control signals for controlling ashift register may be included in the gate control signal (GCS).

The data control signal (DCS) includes a source start pulse (SSP), asource shift clock signal (SSC), a source output enable signal (SOE),and a polarity control signal (POL).

The data driver 130 supplies a data voltage to the data lines (DL) ofthe display panel 110. In detail, the data driver 130 converts the videodata (RGB) provided from the controller 140 into a data voltage, andsupplies the data voltage to the data lines (DL).

The gate driver 120 sequentially supplies a gate pulse (GP) to the gatelines (GL) for 1 frame period. Herein, ‘1 frame’ indicates the period inwhich one image is output through the use of display panel 110. Also,the gate driver 120 supplies a gate-off signal for turning off aswitching device to the gate line (GL) for the remaining period of 1frame in which the gate pulse (GP) is not supplied. Hereinafter, thegate pulse (GP) and the gate-off signal (Goff) are totally referred toas scan signals (SS).

According to one aspect of the present disclosure, the gate driver 120may be provided on the display panel 110. A structure of directlyproviding the gate driver 120 on the display panel 110 may be referredto as Gate-In-Panel (GIP) structure.

FIG. 2 is a circuit diagram illustrating any one pixel (P) of FIG. 1 ,FIG. 3 is a plan view illustrating the pixel (P) of FIG. 2 , and FIG. 4is a cross sectional view along I-I′ of FIG. 3 .

Referring to FIGS. 2, 3 and 4 , the display apparatus 100 according toone aspect of the present disclosure includes a substrate 210, a pixeldriver (PDC) on the substrate 210, and a display device 710 connectedwith the pixel driver (PDC). The pixel driver (PDC) includes thin filmtransistors (TR1, TR2).

The circuit diagram of FIG. 2 corresponds to an equivalent circuitdiagram for one pixel (P1) in the display apparatus 100 comprising anorganic light emitting diode (OLED) functioning as the emission device710. Accordingly, the display apparatus 100 according to one aspect ofthe present disclosure is an organic light emitting diode (OLED) displayapparatus.

The pixel driver (PDC) of FIG. 2 includes a first thin film transistor(TR1) corresponding to a switching transistor, and a second thin filmtransistor (TR2) corresponding to a driving transistor. Also, the pixeldriver (PDC) includes a plurality of signal lines (DL, GL, PL).

According to one aspect of the present disclosure, a gate line (GL) isreferred to as a first signal line, a data line (DL) is referred to as asecond signal line, and a driving power line (PL) is referred to as athird signal line, however, it is not limited to the above structure.The data line (DL) may be the first signal line or the third signalline. Also, the gate line (GL) may be the second signal line or thethird signal line. In the same manner, the driving power line (PL) maybe the first signal line or the second signal line.

Hereinafter, for convenience of explanation, one aspect of the presentdisclosure in which the gate line is the first signal line, the dataline (DL) is the second signal line, and the driving power line (PL) isthe third signal line will be described in detail.

Referring to FIGS. 2 and 3 , the first thin film transistor (TR1) isconnected with the gate line (GL) and the data line (DL), and the firstthin film transistor (TR1) is turned-on or turned-off by the scan signal(SS) supplied through the gate line (GL).

The data line (DL) provides the data voltage (Vdata) to the pixel driver(PDC), and the first thin film transistor (TR1) controls applying thedata voltage (Vdata).

The driving power line (PL) provides a driving voltage (Vdd) to thedisplay device 710, and the second thin film transistor (TR2) controlsthe driving voltage (Vdd). Herein, the driving voltage (Vdd) is a pixeldriving voltage for driving the organic light emitting diode (OLED)corresponding to the display device 710.

When the first thin film transistor (TR1) is turned-on, the data voltage(Vdata), which is supplied through the data line (DL), is supplied to agate electrode (G2) of the second thin film transistor (TR2) connectedwith the emission device 710. The data voltage (Vdata) is charged in afirst capacitor (C1) provided between a source electrode (S2) and thegate electrode (G2) of the second thin film transistor (TR2). The firstcapacitor (C1) is a storage capacitor (Cst).

An amount of current supplied to the organic light emitting diode (OLED)corresponding to the display device 710 through the second thin filmtransistor (TR2) is controlled in accordance with the data voltage(Vdd), whereby it is possible to control a grayscale of light emittedfrom the display device 710.

Referring to FIGS. 3 and 4 , the display apparatus 100 according to oneaspect of the present disclosure includes the first signal line (GL) andthe second signal line (DL) crossing each other on the substrate 210,and also includes a first gate electrode (G1), a first source electrode(S1), a first drain electrode (D1), and a second gate electrode (G2)which are disposed on the same layer as that of the first signal line(GL). Also, the display apparatus 100 according to one aspect of thepresent disclosure includes a first active layer (A1) which is spacedapart from the first gate electrode (G1) and is partially overlappedwith the first gate electrode (G1), a second active layer (A2) which isspaced apart from the second gate electrode (G2) and is partiallyoverlapped with the second gate electrode (G2), and a first electrode711 of the display device 710 connected with the second active layer(A2).

As described above, in case of the display apparatus 100 according toone aspect of the present disclosure, the first signal line is the gateline (GL), and the second signal line is the data line (DL). The gateline (GL) corresponding to the first signal intersects with the dataline (DL) corresponding to the second signal line.

The substrate 210 may be formed of glass or plastic. The substrate 210may be formed of plastic having flexibility, for example, polyimide(PI).

The gate line (GL) corresponding to the first signal line, the firstgate electrode (G1), the first source electrode (S1), the first drainelectrode (D1), and the second gate electrode (G2) are disposed on thesubstrate 210.

The first gate electrode (G1), the first source electrode (S1), thefirst drain electrode (D1), and the second gate electrode (G2) aredisposed on the same layer as that of the gate line (GL).

Also, a first portion (DL1) and a second portion (DL2) included in thedata line (DL) corresponding to the second signal line are disposed onthe same layer as that of the gate line (GL).

Referring to FIGS. 3 and 4 , the data line (DL) includes the firstportion (DL1), the second portion (DL2), and a first connectionelectrode (BR1). The first portion (DL1) of the data line (DL) is spacedapart from the second portion (DL2) of the data line (DL) with the gateline (GL) therebetween.

The first connection electrode (BR1) connects the first portion (DL1) ofthe data line (DL) with the second portion (DL2) of the data line (DL).The first connection electrode (BR1) is spaced apart from the gate line(GL), and at least a portion of the first connection electrode (BR1) maybe overlapped with the gate line (GL).

The gate line (GL), the first gate electrode (G1), the first sourceelectrode (S1), the first drain electrode (D1), the second gateelectrode (G2), and the first and second portions (DL1, DL2) of the dataline (DL) may be manufactured together by the same process using thesame material.

The gate line (GL), the first gate electrode (G1), the first sourceelectrode (S1), the first drain electrode (D1), the second gateelectrode (G2), and the first and second portions (DL1, DL2) of the dataline (DL) may include at least one among aluminum-based metal such asaluminum or aluminum alloy, argentums-based metal such as argentums (Ag)or argentums alloy, copper-based metal such as copper (Cu) or copperalloy, molybdenum-based metal such as molybdenum or molybdenum alloy,chrome (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gateline (GL), the first gate electrode (G1), the first source electrode(S1), the first drain electrode (D1), the second gate electrode (G2) andthe first and second portions (DL1, DL2) of the data line (DL) may havea multi-layered structure including at least two layers with thedifferent physical properties.

According to one aspect of the present disclosure, the first gateelectrode (G1) is connected with any one of the first signal line andthe second signal line. Referring to FIG. 3 , the first gate electrode(G1) is connected with the gate line (GL) corresponding to the firstsignal line. The first gate electrode (G1) may be the region extendedfrom the gate line (GL), or may be one region of the gate line (GL).Referring to FIG. 3 , the first gate electrode (G1) may be the regionextended from the gate line (GL).

According to one aspect of the present disclosure, any one of the firstsource electrode (S1) and the first drain electrode (D1) may beconnected with the second gate electrode (G2), and the other of thefirst source electrode (S1) and the first drain electrode (D1) may beconnected with any one of the first signal line and the second signalline.

In detail, referring to FIG. 3 , the first drain electrode (D1) isconnected with the second gate electrode (G2), and the first sourceelectrode (S1) is connected with the data line (DL) corresponding to thesecond signal line. However, one aspect of the present disclosure is notlimited to the above structure. The first source electrode (S1) may beconnected with the second gate electrode (G2), and the first drainelectrode (D1) may be connected with the data line (DL).

According to one aspect of the present disclosure, the first sourceelectrode (S1) may be one region of the data line (DL), and may be theregion extended from the data line (DL). Referring to FIGS. 3 and 4 ,the first source electrode (S1) may be the region extended from the dataline (DL).

Referring to FIG. 3 , the first drain electrode (D1) and the second gateelectrode (G2) may be formed as one body.

According to one aspect of the present disclosure, the first gateelectrode (G1) and the second gate electrode (G2) respectively protect achannel region 31 of the first active layer (A1) and a channel region 31of the second active layer (A2). Also, according to one aspect of thepresent disclosure, the gate line (GL), the first gate electrode (G1),the first source electrode (S1), the first drain electrode (D1), thesecond gate electrode (G2), the first portion (DL1) of the data line(DL), and the second portion (DL2) of the data line (DL) may bemanufactured by the same process.

Thus, according to one aspect of the present disclosure, it is possiblenot to provide an additional light shielding layer for protecting thechannel region, and to omit an additional process for forming the sourceand drain electrodes. As a result, a structure of the display apparatus100 is simplified, and a manufacturing process of the display apparatus100 is also simplified.

Referring to FIGS. 3 and 4 , a first capacitor electrode (C11) of thefirst capacitor (C) is disposed on the same layer as that of the secondgate electrode (G2). The first capacitor electrode (C11) may be disposedon the same layer as those of the first gate electrode (G1) and thesecond gate electrode (G2). The first capacitor electrode (C11) and thesecond gate electrode (G2) may be formed as one body, and may bemanufactured together with the second gate electrode (G2) by the sameprocess using the same material.

Also, the first capacitor electrode (C11) and the first drain electrode(D1) may be formed as one body, and may be manufactured together withthe first drain electrode (D1) by the same process using the samematerial.

The display apparatus 100 according to one aspect of the presentdisclosure further includes a third signal line (PL). The third signalline (PL) may intersect with any one of the first signal line (GL) andthe second signal line (DL). Referring to FIGS. 3 and 4 , the drivingpower line (PL) corresponding to the third signal line intersects withthe gate line (GL) corresponding to the first signal line.

The driving power line (PL) includes a first portion (PL1), a secondportion (PL2), and a second connection electrode (BR2). The firstportion (PL1) of the driving power line (PL) and the second portion(PL2) of the driving power line (PL) are disposed on the same layer asthat of the gate line (GL). The first portion (PL1) of the driving powerline (PL) is spaced apart from the second portion (PL2) of the drivingpower line (PL) with the gate line (GL) therebetween. The secondconnection electrode (BR2) connects the first portion (PL1) of thedriving power line (PL) with the second portion (PL2) of the drivingpower line (PL). The second connection electrode (BR2) is spaced apartfrom the gate line (GL), and at least a portion of the second connectionelectrode (BR2) is overlapped with the gate line (GL).

Referring to FIG. 3 , the second drain electrode (D2) is disposed on thesubstrate 210. The second drain electrode (D2) may be one region of thedriving power line (PL), or may be the region extended from the drivingpower line (PL). Referring to FIGS. 3 and 4 , the second drain electrode(D2) may be the region extended from the driving power line (PL).

A gate insulating film 230 is disposed on the gate line (GL), the firstgate electrode (G1), the first source electrode (S1), the first drainelectrode (D1), the second gate electrode (G2), the first portion (DL1)of the data line (DL), the second portion (DL2) of the data line (DL),the first capacitor electrode (C11) of the first capacitor (C1), thefirst portion (PL1) of the driving power line (PL), the second portion(PL2) of the driving power line (PL), and the second drain electrode(D2).

The gate insulating film 230 has the insulating properties. For example,the gate insulating film 230 may be formed of an insulating material,for example, silicon oxide or silicon nitride.

The first active layer (A1) and the second active layer (A2) aredisposed on the gate insulating film 230. The first active layer (A1) isspaced apart from the first gate electrode (G1), and at least a portionof the first active layer (A1) is overlapped with the first gateelectrode (G1). The second active layer (A2) is spaced apart from thesecond gate electrode (G2), and at least a portion of the second activelayer (A2) is overlapped with the second gate electrode (G2).

According to one aspect of the present disclosure, the first activelayer (A1) and the second active layer (A2) are disposed on the firstgate electrode (G1) and the second gate electrode (G2), respectively.The first active layer (A1) and the second active layer (A2) may bemanufactured together by the same mask process.

According to one aspect of the present disclosure, the first activelayer (A1) and the second active layer (A2) may include an oxidesemiconductor material. For example, the first active layer (A1) and thesecond active layer (A2) may include at least one among IZO(InZnO)-basedoxide semiconductor, IGO(InGaO)-based oxide semiconductor, GO(GaO)-basedoxide semiconductor, ITO(InSnO)-based oxide semiconductor,IGZO(InGaZnO)-based oxide semiconductor, IGTO(InGaSnO)-based oxidesemiconductor, IGZTO (InGaZnSnO)-based oxide semiconductor, GZTO(GaZnSnO)-based oxide semiconductor, GZO (GaZnO)-based oxidesemiconductor, and ITZO (InSnZnO)-based oxide semiconductor. However,one aspect of the present disclosure is not limited to the abovematerials. The first and second active layers (A1, A2) may be formed ofother oxide semiconductor materials generally known to those in the art.

The first active layer (A1) functions as an active layer of the firstthin film transistor (TR1), and the second active layer (A2) functionsas an active layer of the second thin film transistor (TR2).

By a selective conductivity providing process, some regions of the firstand second active layers (A1, A2) become conducting regions.

Some regions of the first and second active layers (A1, A2), which areoverlapped with the first and second gate electrodes (G1, G2), are notprovided with conductivity, and thus do not become the conductingregions, but become the channel region 31. Some regions of the first andsecond active layer (A1, A2), which are not overlapped with the firstand second gate electrodes (G1, G2), are provided with conductivity, andthus become the conducting regions 32 and 33. Generally, the conductingregions 32 and 33 may be formed at both sides with respect to thechannel region 31.

According to one aspect of the present disclosure, some regions of thefirst and second active layers (A1, A2) may be the conducting regions bya doping process using dopant. In this case, doped regions become theconducting regions. For the doping process, at least one of boron (B)ion, phosphorous (P) ion, and fluorine (F) ion may be used.

However, one aspect of the present disclosure is not limited to theabove. Herein, some regions of the first and second active layers (A1,A2) may be provided with conductivity by a dry etching process, or aphoto irradiation process. For example, ultraviolet ray is irradiatedonto the substrate 210, whereby some regions of the first and secondactive layers (A1, A2), which are not overlapped with the first andsecond gate electrodes (G1, G2), may be provided with conductivity, andthus may be the conducting regions. If ultraviolet ray is irradiatedonto the substrate 210, the first and second gate electrodes (G1, G2)function as a mask for blocking ultraviolet ray, whereby the otherregions of the first and second active layers (A1, A2), which areoverlapped with the first and second gate electrodes (G1, G2), are notprovided with conductivity, and thus remains as the regions having thesemiconductor properties. As a result, the regions of the first andsecond active layers (A1, A2), which are overlapped with the first andsecond gate electrodes (G1, G2), may be the channel region 31.

Any one of the conducting regions 32 and 33 of the first and secondactive layers (A1, A2) becomes a source region 32, and the other becomesa drain region 33. The source region 32 serves as a source connectionregion connected with the source electrode (S1, S2), or the sourceregion 32 itself serves as the source electrode (S1, S2). The drainregion 33 serves as a drain connection region connected with the drainelectrode (D1, D2), or the drain region 33 itself serves as the drainelectrode (D1, D2).

The source region 32 and the drain region 33 shown in the drawings aredistinguished from each other, for convenience of explanation. However,the source region 32 and the drain region 33 may be usedinterchangeably. The source region 32 may become the drain region 33,and the drain region 33 may become the source region 32. Also, thesource region 32 may become the source electrode (S1, S2) and the drainelectrode (D1, D2), and the drain region 33 may become the drainelectrode (D1, D2) and the source electrode (S1, S2).

The first active layer (A1) contacts the first source electrode (S1) andthe first drain electrode (De) via a contact hole (H1, H2) formed in thegate insulating film 230.

In detail, the source region 32 of the first active layer (A1) contactsthe first source electrode (S1) via a first contact hole (H1) formed inthe gate insulating film 230. The drain region 33 of the first activelayer (A1) contacts the first drain electrode (D1) via a second contacthole (H2) formed in the gate insulating film 230.

The drain region 33 of the second active layer (A2) is connected withthe second drain electrode (D2) via a third contact hole (H3) formed inthe gate insulating film 230.

According to one aspect of the present disclosure, the source region 32of the second active layer (A2) serves as the second source electrode(S2).

A protection layer 250 is disposed on the first and second active layers(A1, A2). The protection layer 250 is provided to planarize an uppersurface of the first and second active layers (A1, A2), and to protectthe pixel driver (PDC), whereby the protection layer 250 may be referredto as a planarization layer.

Referring to FIG. 4 , the display device 710 is disposed on theprotection layer 250. In detail, the first electrode 711 of the displaydevice 710 is disposed on the protection layer 250, and an emissionlayer 712 and a second electrode 713 are sequentially disposed on thefirst electrode 711, to thereby form the display device 710. In FIG. 4 ,the first pixel 711 is a pixel electrode, and the second electrode 713is a common electrode.

The first electrode 711 of the display device 710 is connected with thesecond active layer (A2). In detail, the first electrode 711 of thedisplay device 710 is connected with the second source electrode (S2)via a fourth contact hole (H4), whereby the first electrode 711 of thedisplay device 710 may be electrically connected with the second activelayer (A2). The fourth contact hole (H4) is formed in the protectionlayer 250.

Also, the first connection electrode (BR1) and the second connectionelectrode (BR2) are disposed on the protection layer 250.

The first connection electrode (BR1) is disposed on the same layer asthat of the first electrode 711, and the first connection electrode(BR1) is connected with the first and second portions (DL1, DL2) of thedata line (DL) corresponding to the second signal line via fifth andsixth contact holes (H5, H6).

The second connection electrode (BR2) is disposed on the same layer asthat of the first electrode 711, and the second connection electrode(BR2) is connected with the first and second portions (PL1, PL2) of thedriving power line (PL) corresponding to the third signal line viaseventh and eighth contact holes (H7, H8).

The first connection electrode (BR1) and the second connection electrode(BR2) are formed of the same material as that of the first electrode711. The first connection electrode (BR1) and the second connectionelectrode (BR2) are manufactured together with the first electrode 711by the same mask process.

According to one aspect of the present disclosure, one portion of thefirst electrode 711 of the display device 710, which is overlapped withthe first capacitor electrode (C11), may function as a second capacitorelectrode (C12). Thus, the first capacitor electrode (C11) overlaps withthe first electrode 711 of the display device 710 so that it is possibleto form the first capacitor (C1).

A bank layer 750 is disposed on the periphery of the first electrode711. The bank layer 750 defines an emission area of the display device710.

The emission layer 712 is disposed on the first electrode 711. Herein,the emission layer 712 is an organic emission layer including an organicmaterial. The second electrode 713 is disposed on the emission layer712. Accordingly, it is possible to complete the display device 710.

The display device 710 shown in FIG. 4 corresponds to an organic lightemitting diode (OLED). Thus, the display apparatus 100 according to oneaspect of the present disclosure corresponds to an organic lightemitting diode (OLED) display apparatus.

According to one aspect of the present disclosure, the first thin filmtransistor (TR1) includes the first active layer (A1), the first gateelectrode (A1), the first source electrode (S1), and the first drainelectrode (D1). Also, the second thin film transistor (TR2) includes thesecond active layer (A2), the second gate electrode (A2), the secondsource electrode (S2), and the second drain electrode (D2).

According to one aspect of the present disclosure, as shown in FIG. 4 ,the first gate electrode (G1) is disposed between the substrate 210 andthe first active layer (A1), and the second gate electrode (G2) isdisposed between the substrate 210 and the second active layer (A2).According to one aspect of the present disclosure, the first thin filmtransistor (TR1) and the second thin film transistor (TR2) may have abottom gate structure where the gate electrode (G1, G2) is disposedbelow the active layer (A1, A2).

Meanwhile, in contrast to the bottom gate structure, a structure of thethin film transistor where the gate electrode (G1, G2) is disposed abovethe active layer (A1, A2) is referred to as a top gate structure.

In case of the thin film transistor of the bottom gate structure, thenumber of deposited layers is relatively smaller in comparison to thatof the top gate structure so that it is possible to simplify amanufacturing process, and to decrease an occupying size of the thinfilm transistor. Thus, the aspect of the present disclosure may beusefully applied to a high resolution display apparatus with highdensity of the thin film transistor.

FIG. 5 is a cross sectional view illustrating a pixel of a displayapparatus 200 according to another aspect of the present disclosure.

In the display apparatus 200 shown in FIG. 5 , an active layer (A1, A2)has a multi-layered structure. Referring to FIG. 5 , a first activelayer (A1) includes a first oxide semiconductor layer (A11) on a firstgate electrode (G1), and a second oxide semiconductor layer (A12) on thefirst oxide semiconductor layer (A11). The second active layer (A2)includes a first oxide semiconductor layer (A21) on a second gateelectrode (G2), and a second oxide semiconductor layer (A22) on thefirst oxide semiconductor layer (A21).

According to one aspect of the present disclosure, the second oxidesemiconductor layer (A12, A22) serves as a protection layer configuredto protect the first oxide semiconductor layer (A11, A21), and the firstoxide semiconductor layer (A11, A21) serves as a channel layer.Typically, a channel of the active layer (A1, A2) is provided in thefirst oxide semiconductor layer (A11, A21). However, one aspect of thepresent disclosure is not limited to the above. A channel of the activelayer (A1, A2) may be provided in the second oxide semiconductor layer(A12, A22).

For improvement of the film stability, the second oxide semiconductorlayer (A12, A22), which serves as the protection layer, may includegallium (Ga). According to one aspect of the present disclosure, thesecond oxide semiconductor layer (A12, A22) may include at least oneamong IGZO(InGaZnO)-based oxide semiconductor material, IGO(InGaO)-basedoxide semiconductor material, IGTO(InGaSnO)-based oxide semiconductormaterial, GZO (GaZnO)-based oxide semiconductor material, IGZTO(InGaZnSnO)-based oxide semiconductor material, GZTO (GaZnSnO)-basedoxide semiconductor material, and GO(GaO)-based oxide semiconductormaterial. However, one aspect of the present disclosure is not limitedto the above materials. The second oxide semiconductor layer (A12, A22)may be formed of other oxide semiconductor materials generally known tothose in the art.

The first oxide semiconductor layer (A11, A21) may include at least oneamong IZO(InZnO)-based oxide semiconductor, IGO(InGaO)-based oxidesemiconductor, ITO(InSnO)-based oxide semiconductor, IGZO(InGaZnO)-basedoxide semiconductor, IGZTO (InGaZnSnO)-based oxide semiconductor, GZTO(GaZnSnO)-based oxide semiconductor, GZO (GaZnO)-based oxidesemiconductor, and ITZO (InSnZnO)-based oxide semiconductor. However,one aspect of the present disclosure is not limited to the abovematerials. The first oxide semiconductor layer (A11, A21) may be formedof other oxide semiconductor materials generally known to those in theart.

The first oxide semiconductor layer (A11, A21) has the electricalproperties which are greater than that of the second oxide semiconductorlayer (A12, A22), and the second oxide semiconductor layer (A12, A22)has the greater film stability than that of the first oxidesemiconductor layer (A11, A21). Also, according to one aspect of thepresent disclosure, the first oxide semiconductor layer (A11, A21) hasthe greater tolerance to etching than that of the second oxidesemiconductor layer (A12, A22), whereby the first active layer (A1) andthe second active layer (A2) may have a tapered shape.

FIG. 6 is a cross sectional view illustrating a pixel of a displayapparatus 300 according to another aspect of the present disclosure.

Referring to FIG. 6 , a first connection electrode (BR1) includes atransparent conductive oxide (TCO) layer 271 which is formed of the samematerial as that of a first electrode 711 of a display device 710, and ametal layer 272 on the TCO layer 271.

Also, a second connection electrode (BR2) includes a transparentconductive oxide (TCO) layer 271 which is formed of the same material asthat of the first electrode 711 of the display device 710, and a metallayer 272 on the TCO layer 271.

The TCO layer 271 may include at least one among ITO(InSnO), ZnO, In₂O₃,MgO and SnO₂. However, one aspect of the present disclosure is notlimited to the above. The TCO layer 271 may be formed of othertransparent conductive oxide materials generally known to those in theart.

The first electrode 711 of the display device 710, the first connectionelectrode (BR1), and the second connection electrode (BR2), which areshown in FIG. 6 , may be manufactured at the same time by a patterningprocess using a halftone mask.

For example, a first layer of a transparent conductive oxide materialand a second layer of a metal material are sequentially provided on aprotection layer 250, and then the patterning process using the halftonemask is carried out so that only the layer of the transparent conductiveoxide material remains in the area of the first electrode 711 of thedisplay device 710, and both the layer of the transparent conductiveoxide material and the layer of the metal material remain in the area ofthe first connection electrode (BR1) and the second connection electrode(BR2). According to the above method, it is possible to manufacture thefirst electrode 711 of the display device 710, the first connectionelectrode (BR1), and the second connection electrode (BR2) at the sametime.

FIG. 7 is a plan view illustrating a pixel of a display apparatus 400according to another aspect of the present disclosure. FIG. 8 is a crosssectional view along II-II′ of FIG. 7 .

Referring to FIGS. 7 and 8 , a second capacitor electrode (C12)connected with a second source electrode (S2) is disposed on a gateinsulating film 230. The second capacitor electrode (C12) may be formedas one body with a second active layer (A2). Also, the second capacitorelectrode (C12) may be connected with a first electrode 711 of a displaydevice 710.

According to another aspect of the present disclosure, some portions ofa conducting region 32 and 33 of the second active layer (A2) may be thesecond capacitor electrode (C12). As shown in FIGS. 7 and 8 , a sourceconnection region 32 included in the conducting region 32 and 33 of thesecond active layer (A2) extends so that the source connection region 32is overlapped with a first capacitor electrode (C11) of a firstcapacitor (C1), whereby it may serve as the second capacitor electrode(C12). The second capacitor electrode (C12) is overlapped with the firstcapacitor electrode (C11), to thereby form the first capacitor (C1).

FIG. 9 is a plan view illustrating pixels (P1, P2) of a displayapparatus 500 according to another aspect of the present disclosure.

In FIG. 9 , a data line (DL) is a first signal line, and a gate line(GL) is a second signal line.

Referring to FIG. 9 , the data line (DL) corresponding to the firstsignal line and the gate line (GL) corresponding to the second signalline are disposed on a substrate 210. The data line (DL) correspondingto the first signal line and the gate line (GL) corresponding to thesecond signal line intersect with each other.

The gate line (GL) includes a first portion (GL1), a second portion(GL2), and a first connection electrode (BR21). The first portion (GL1)of the gate line (GL) is spaced apart from the second portion (GL2) ofthe gate line (GL) with the data line (DL) therebetween. Referring toFIG. 9 , the first portion (GL1) of the gate line (GL) is disposed in afirst pixel (P1), and the second portion (GL2) of the gate line (GL) isdisposed in a second pixel (P2).

The first connection electrode (BR21) connects the first portion (GL1)of the gate line (GL) with the second portion (GL2) of the gate line(GL). The first connection electrode (BR21) is spaced apart from thedata line (GL), and at least a portion of the first connection electrode(BR21) may be overlapped with the data line (DL).

A second connection electrode (BR22) of FIG. 9 may connect the firstportion (GL1) of the gate line (GL) disposed in the first pixel (P1)with one portion of the gate line (GL) disposed in the left-sided pixelof the drawing. Also, a third connection electrode (BR23) of FIG. 9 mayconnect the second portion (GL2) of the gate line (GL) disposed in thesecond pixel (P2) with one portion of the gate line (GL) disposed in theright-sided pixel of the drawing.

Referring to FIG. 9 , the display apparatus 500 according to anotheraspect of the present disclosure may further include a driving powerline (PL). In another aspect of the present disclosure, the drivingpower line (PL) may be referred to as a third signal line.

The driving power line (PL) corresponding to the third signal lineintersects with the gate line (GL) corresponding to the second signalline. The first connection electrode (BR21) is spaced apart from thedriving power line (PL), and at least a portion of the first connectionelectrode (BR21) may be overlapped with the driving power line (PL).

FIG. 10 is a circuit diagram for any one pixel of a display apparatus600 according to another aspect of the present disclosure. FIG. 10 is anequivalent circuit diagram for a pixel (P) of an organic light emittingdisplay apparatus.

The pixel (P) of the display apparatus 600 shown in FIG. 10 includes anorganic light emitting diode (OLED) corresponding to a display device710, and a pixel driver (PDC) configured to drive the display device710. The display device 710 is connected with the pixel driver (PDC).

In the pixel (P), there are signal lines (DL, GL, PL, RL, SCL)configured to supply signals to the pixel driver (PDC).

A data voltage (Vdata) is supplied to a data line (DL), a scan signal(SS) is supplied to a gate line (GL), a driving voltage (Vdd) fordriving the pixel is supplied to a driving power line (PL), a referencevoltage (Vref) is supplied to a reference line (RL), and a sensingcontrol signal (SCS) is supplied to a sensing control line (SCL).

Referring to FIG. 10 , when the gate line of the (n)th pixel (P) isreferred to as “GL_(n)”, the gate line of the neighboring (n−1)th pixel(P) is “GL_(n-1)”, and “GL_(n-1)” corresponding to the gate line of the(n−1)th pixel (P) serves as the sensing control line (SCL) of the (n)thpixel (P).

For example, as shown in FIG. 10 , the pixel driver (PDC) includes afirst thin film transistor (TR1, switching transistor) connected withthe gate line (GL) and the data line (DL), a second thin film transistor(TR2, driving transistor) configured to control a level of current whichis provided to the display device 710 in accordance with the datavoltage (Vdata) transmitted through the first thin film transistor(TR1), and a third thin film transistor (TR3, reference transistor)configured to sense the properties of the second thin film transistor(TR2).

A first capacitor (C1) is positioned between the display device 710 anda gate electrode (G2) of the second thin film transistor (TR2). Thefirst capacitor (C1) is referred to as a storage capacitor (Cst).

According as the first thin film transistor (TR1) is turned-on by thescan signal (SS) supplied to the gate line (GL), the first thin filmtransistor (TR1) transmits the data voltage (Vdata), which is suppliedto the data line (DL), to the gate electrode (G2) of the second thinfilm transistor (TR2).

The third thin film transistor (TR3) is connected with the referenceline (RL) and a first node (n1) between the display device 710 and thesecond thin film transistor (TR2). The third thin film transistor (TR3)is turned-on or turned-off by the sensing control signal (SCS), and thethird thin film transistor (TR3) senses the properties of the secondthin film transistor (TR2) corresponding the driving transistor for asensing period.

A second node (n2) connected with the gate electrode (G2) of the secondthin film transistor (TR2) is connected with the first thin filmtransistor (TR1). The first capacitor (C1) is formed between the secondnode (n2) and the first node (n1).

When the first thin film transistor (TR1) is turned-on, the data voltage(Vdata) supplied through the data line (DL) is supplied to the gateelectrode (G2) of the second thin film transistor (TR2). The firstcapacitor (C1) formed between a source electrode (S2) and the gateelectrode (G2) of the second thin film transistor (TR2) is charged withthe data voltage (Vdata).

When the second thin film transistor (TR2) is turned-on, the current issupplied to the display device 710 through the second thin filmtransistor (TR2) by the driving voltage (Vdd) for driving the pixel,whereby light is emitted from the display device 710.

FIG. 11 is a circuit diagram illustrating a pixel (P) applied to adisplay apparatus 700 according to another aspect of the presentdisclosure.

The pixel (P) of the display apparatus 700 shown in FIG. 11 includes anorganic light emitting diode (OLED) corresponding to a display device710, and a pixel driver (PDC) configured to drive the display device710. The display device 710 is connected with the pixel driver (PDC).

The pixel driver (PDC) includes thin film transistors (TR1, TR2, TR3,TR4).

In the pixel (P), there are signal lines (DL, EL, GL, PL, SCL, RL)configured to supply driving signals to the pixel driver (PDC).

In comparison to the pixel (P) of FIG. 10 , the pixel (P) of FIG. 11further includes an emission control line (EL). An emission controlsignal (EM) is supplied to the emission control line (EL).

Also, in comparison to the pixel driver (PDC) of FIG. 10 , the pixeldriver (PDC) of FIG. 11 further includes a fourth thin film transistor(TR4) corresponding to an emission control transistor configured tocontrol a light emission time point of the second thin film transistor(TR2).

Referring to FIG. 11 , when the gate line of the (n)th pixel (P) isreferred to as “GL_(n)”, the gate line of the neighboring (n−1)th pixel(P) is “GL_(n-1)”, and “GL_(n-1)” corresponding to the gate line of the(n−1)th pixel (P) serves as the sensing control line (SCL) of the (n)thpixel (P).

A first capacitor (C1) is positioned between the display device 710 anda gate electrode (G2) of the second thin film transistor (TR2). Also, asecond capacitor (C2) is positioned between one electrode of the displaydevice 710 and a terminal supplied with a driving voltage (Vdd) amongterminals of the fourth thin film transistor (TR4).

According as the first thin film transistor (TR1) is turned-on by thescan signal (SS) supplied to the gate line (GL), the first thin filmtransistor (TR1) transmits the data voltage (Vdata), which is suppliedto the data line (DL), to the gate electrode (G2) of the second thinfilm transistor (TR2).

The third thin film transistor (TR3) is connected with a reference line(RL). The third thin film transistor (TR3) is turned-on or turned-off bythe sensing control signal (SC S), and the third thin film transistor(TR3) senses the properties of the second thin film transistor (TR2)corresponding the driving transistor for a sensing period.

The fourth thin film transistor (TR4) transmits the driving voltage(Vdd) to the second thin film transistor (TR2), or blocks the drivingvoltage (Vdd) in accordance with the emission control signal (EM). Whenthe fourth thin film transistor (TR4) is turned-on, the current issupplied to the second thin film transistor (TR2), whereby light isemitted from the display device 710.

The pixel driver (PDC) according to another aspect of the presentdisclosure may be formed in various structures in addition to theabove-described structure. For example, the pixel driver (PDC) mayinclude five thin film transistors or more.

Hereinafter, a method for manufacturing the display apparatus 100according to one aspect of the present disclosure will be described indetail as follows.

FIGS. 12A and 12B are respective plane and cross sectional views for amanufacturing process of the display apparatus 100 according to oneaspect of the present disclosure.

Referring to FIGS. 12A and 12B, the gate line (GL) corresponding to thefirst signal line, the first gate electrode (G1), the first sourceelectrode (S1), the first drain electrode (D1), the second gateelectrode (G2), and the first portion (DL1) and second portion (DL2) ofthe data line (DL) corresponding to the second signal line are providedon the substrate 210. Also, the first portion (PL1) and second portion(PL2) of the driving power line (PL) corresponding to the third signalline is provided on the substrate 210, and the second drain electrode(D2) extending from the driving power line (PL) is also provided on thesubstrate 210. In this case, a mask process is carried out.

Then, referring to FIGS. 13A and 13B, the gate insulating film 230 isprovided on the gate line (GL), the first gate electrode (G1), the firstsource electrode (S1), the first drain electrode (D1), the second gateelectrode (G2), the first portion (DL1) and second portion (DL2) of thedata line (DL), the first portion (PL1) and second portion (PL2) of thedriving power line (PL), and the second drain electrode (D2).

The first contact hole (H1), the second contact hole (H2), and the thirdcontact hole (H3) are provided on the gate insulating film 230. In thiscase, a mask process is carried out.

Then, referring to FIGS. 14A, 14B, 14C, 14D and 14E, the first activelayer (A1) and the second active layer (A2) are provided on the gateinsulating film 230. At least a portion of the first active layer (A1)is overlapped with the first gate electrode (G1), and at least a portionof the second active layer (A2) is overlapped with the second gateelectrode (G2).

Referring to one aspect of the present disclosure, the first activelayer (A1) and the second active layer (A2) may be formed by an etchingprocess using a halftone mask 610.

FIGS. 14B to 14E respectively show steps for the etching process usingthe halftone mask 610.

In detail, referring to FIG. 14 , an oxide semiconductor material layer30 is provided on the gate insulating film 230, and a photoresist layer510 is disposed on the oxide semiconductor material layer 30. Also, thehalftone mask 610 is disposed above the photoresist layer 510. Thehalftone mask 610 includes a light blocking portion 611, a transmittingportion 612, and a semi-transmitting portion 613.

The halftone mask 610 is disposed while being spaced apart from thephotoresist layer 510, and light (L1) is irradiated thereonto throughthe halftone mask 610, whereby a selective exposure for the photoresistlayer 510 is performed.

Referring to FIG. 14C, the selectively-exposed photoresist layer 510 isdeveloped, to thereby form a plurality of photoresist patterns 511 and512. Also, the oxide semiconductor material layer 30 is patterned by anetching process using the photoresist pattern 511 and 512 as a mask, tothereby form the first active layer (A1) and the second active layer(A2).

Referring to FIG. 14D, the photoresist pattern 511 and 512 isadditionally ashed so that the photoresist pattern 511 and 512 remainsonly above the channel region 33 of the first active layer (A1) and thesecond active layer (A2), and the other portions of the first activelayer (A1) and the second active layer (A2) are exposed. Under theseconditions, some portions of the first active layer (A1) and the secondactive layer (A2) may be selectively provided with conductivity to beconducting regions.

The above step for selectively providing conductivity to the firstactive layer (A1) and the second active layer (A2) to make theconducting regions in the first active layer (A1) and the second activelayer (A2) may include a doping process using dopant.

For example, some regions of the first active layer (A1) and the secondactive layer (A2) may be selectively provided with conductivity, andthus become the conducting regions. In this case, doped regions becomethe conducting regions, to thereby provide the conducting region 32 and33. For the doping process, at least one of boron (B) ion, phosphorous(P) ion, and fluorine (F) ion may be used.

However, one aspect of the present disclosure is not limited to theabove. Herein, a region of the first active layers (A1) and a region ofthe second active layer (A2) may be provided with conductivity to be theconducting regions by a dry etching process, or a photo irradiationprocess.

For example, as shown in FIG. 14 , ultraviolet ray (L2) is irradiatedonto the substrate 210, whereby some regions of the first and secondactive layers (A1, A2), which are not overlapped with the first andsecond gate electrodes (G1, G2), may be the conducting regions. Ifultraviolet ray (L2) is irradiated onto the substrate 210, the first andsecond gate electrodes (G1, G2) function as a mask for blockingultraviolet ray, whereby the other regions of the first and secondactive layers (A1, A2), which are overlapped with the first and secondgate electrodes (G1, G2), are not provided with conductivity, and becomethe regions having the semiconductor properties. As a result, theregions of the first and second active layers (A1, A2), which areoverlapped with the first and second gate electrodes (G1, G2), may bethe channel region 31.

As a result, as shown in FIG. 14E, it is possible to provide the firstactive layer (A1) and the second active layer (A2) which respectivelyhave the channel region 31 and the conducting region 32 and 33.

Then, referring to FIGS. 15A and 15B, the protection layer 250 isprovided on the first active layer (A1) and the second active layer(A2). The fourth contact hole (H4), the fifth contact hole (H5), thesixth contact hole (H6), the seventh contact hole (H7), and the eighthcontact hole (H8) are formed in the protection layer 250.

The fourth contact hole (H4) penetrates through the protection layer250. The fifth contact hole (H5), the sixth contact hole (H6), theseventh contact hole (H7), and the eighth contact hole (H8) penetratethrough the protection layer 250 and the gate insulating film 230. Forthe formation of the contact holes (H4, H5, H6, H7 and H8), a maskprocess is carried out.

Then, referring to FIGS. 16A and 16B, the first connection electrode(BR1) is provided on the protection layer 250, and the first connectionelectrode (BR1) is disposed on the same layer as that of the firstelectrode 711 of the display device 710. Also, the second connectionelectrode (BR2) is disposed on the protection layer 250.

The first electrode 711 of the display device 710 is connected with thesecond active layer (A2). In detail, the first electrode 711 of thedisplay device 710 is connected with the second source electrode (S2)via the fourth contact hole (H4), whereby the first electrode 711 of thedisplay device 710 may be electrically connected with the second activelayer (A2).

The first connection electrode (BR1) is disposed on the same layer asthe first electrode 711, and the first connection electrode (BR1) isconnected with the first portion (DL1) and second portion (DL2) of thedata line (DL) corresponding to the second signal line via the contacthole (H5, H6). In detail, the first connection electrode (BR1) isconnected with the first portion (DL1) and second portion (DL2) of thedata line (DL) via the fifth contact hole (H5) and sixth contact hole(H6) penetrating through the protection layer 250 and the gateinsulating film 230.

The second connection electrode (BR2) is disposed on the same layer asthat of the first electrode 711, and the second connection electrode(BR2) is connected with the first portion (PL1) and second portion (PL2)of the driving power line (PL) corresponding to the third signal linevia the seventh contact hole (H7) and eighth contact hole (H8).

The first connection electrode (BR1) and the second connection electrode(BR2) are formed of the same material as that of the first electrode711. The first connection electrode (BR1) and the second connectionelectrode (BR2) may be manufactured together with the first electrode711 by the same mask process.

Referring to FIG. 16C, the bank layer 750 is disposed on the peripheryof the first electrode 711. The bank layer 750 defines the emission areaof the display device 710.

Referring to FIG. 16D, the emission layer 712 is disposed on the firstelectrode 711. Herein, the emission layer 712 is the organic emissionlayer including the organic material.

Referring to FIG. 16E, the second electrode 713 is disposed on theemission layer 712. Accordingly, it is possible to complete the displaydevice 710.

According to one aspect of the present disclosure, the first gateelectrode (G1) is connected with the gate line (GL) corresponding to thefirst signal line. Also, the first drain electrode (D1) is connectedwith the second gate electrode (G2). The first source electrode (S1) isconnected with the data line (DL) corresponding to the second signalline.

Also, referring to FIG. 6 , the process of forming the first electrode711 and the first connection electrode (BR1) may include steps offorming the transparent conductive oxide (TCO) layer on the protectionlayer 250, forming the metal layer on the TCO layer, and patterning theTCO layer and the metal layer. The metal layer is removed from the areaof the first electrode 711 of the display device 710.

In more detail, the first electrode 711 of the display device 710, thefirst connection electrode (BR1), and the second connection electrode(BR2) shown in FIG. 6 may be manufactured at the same time by thepatterning process using the halftone mask. For example, the first layerof the transparent conductive oxide material and the second layer of themetal material are sequentially provided on the protection layer 250,and the patterning process using the halftone mask is carried out sothat only the layer of the transparent conductive oxide material remainsin the area of the first electrode 711 of the display device 710, andboth the layer of the transparent conductive oxide material and thelayer of the metal material remain in the area of the first connectionelectrode (BR1) and the second connection electrode (BR2).

According to one aspect of the present disclosure, the signal lines areprovided in the same layer, and it is unnecessary to provide anadditional light shielding layer for protecting the oxide semiconductorlayer so that it is possible to simplify a structure of the displayapparatus, and also to simplify a manufacturing process of the displayapparatus.

According to one aspect of the present disclosure, the conductingregions of the oxide semiconductor layer formed by the selectiveconductivity providing process of the oxide semiconductor layer serve asthe connection region between the signal line and the oxidesemiconductor layer so that it is unnecessary to provide a process forforming additional source and drain electrodes. Thus, in case of themanufacturing process of the display apparatus according to one aspectof the present disclosure, an additional mask process for forming thesource and drain electrodes of the thin film transistor is not requiredso that it is possible to simplify a structure of the display apparatus,and also to simplify a manufacturing process of the display apparatus.

It will be apparent to those skilled in the art that the presentdisclosure described above is not limited by the above-described aspectsand the accompanying drawings and that various substitutions,modifications, and variations can be made in the present disclosurewithout departing from the spirit or scope of the disclosures.Consequently, the scope of the present disclosure is defined by theaccompanying claims, and it is intended that all variations ormodifications derived from the meaning, scope, and equivalent concept ofthe claims fall within the scope of the present disclosure.

What is claimed is:
 1. A method for manufacturing a display apparatuscomprising: providing a first signal line, a first gate electrode, afirst source electrode, a first drain electrode, a second gateelectrode, and a first portion and a second portion of a second signalline on a substrate; providing a gate insulating film on the firstsignal line, the first gate electrode, the first source electrode, thefirst drain electrode, the second gate electrode, and the first portionand the second portion of the second signal line; providing a firstactive layer and a second active layer on the gate insulating film,wherein at least a portion of the first active layer is overlapped withthe first gate electrode, and at least a portion of the second activelayer is overlapped with the second gate electrode; selectivelyproviding conductivity to the first active layer and the second activelayer to make conducting regions in the first active layer and thesecond active layer; providing a protection layer on the first activelayer and the second active layer; and providing a first connectionelectrode and a first electrode of a display device on the protectionlayer, wherein the first connection electrode connects the first portionof the second signal line with the second portion of the second signalline, wherein the first gate electrode is connected with one of thefirst signal line and the second signal line, one of the first sourceelectrode and the first drain electrode is connected with the secondgate electrode, and another one of the first source electrode and thefirst drain electrode is connected with the other of the first signalline and the second signal line.
 2. The method according to claim 1,wherein the process of selectively providing conductivity to the firstactive layer and the second active layer includes a doping process usingdopant.
 3. The method according to claim 1, wherein the process ofproviding the first connection electrode and the first electrode of thedisplay device includes: providing a transparent conductive oxide (TCO)layer on the protection layer; providing a metal layer on thetransparent conductive oxide layer; and patterning the transparentconductive oxide layer and the metal layer, wherein the metal layer isremoved from the area for the first electrode of the display device. 4.The method according to claim 1, wherein both the first source electrodeand the first drain electrode are formed between the substrate and thefirst active layer.
 5. The method according to claim 1, wherein one ofthe first signal line and the second signal line is a gate line, andanother one of the first signal line and the second signal line is adata line.
 6. The method according to claim 1, wherein one of the firstsource electrode and the first drain electrode is formed as one bodywith the second gate electrode.
 7. The method according to claim 1,wherein the first active layer is disposed on the gate insulating film,and the first active layer contacts the first source electrode and thefirst drain electrode via contact holes formed in the gate insulatingfilm.
 8. The method according to claim 7, wherein the first active layerincludes a channel region and a source region and a drain regionconnected with the channel region, and wherein the source regioncontacts the first source electrode, and the drain region contacts thefirst drain electrode.
 9. The method according to claim 8, wherein thesource region and the drain region are formed when selectively providingconductivity to the first active layer and the second active layer. 10.The method according to claim 1, wherein the first connection electrodeand the first electrode of the display device are formed at a same timeby a same mask process.
 11. The method according to claim 1, wherein thefirst connection electrode includes: a transparent conductive oxidelayer formed of a same material as the first electrode of the displaydevice; and a metal layer disposed on the transparent conductive oxidelayer.
 12. The method according to claim 1, wherein the first gateelectrode is formed between the substrate and the first active layer,and the second gate electrode is formed between the substrate and thesecond active layer.
 13. The method according to claim 1, wherein eachof the first active layer and the second active layer is formed by anoxide semiconductor material.
 14. The method according to claim 1,further comprising forming a first capacitor electrode on a same layeras the second gate electrode.
 15. The method according to claim 14,wherein the first capacitor electrode is formed as one body with thesecond gate electrode.
 16. The method according to claim 14, wherein thefirst capacitor electrode is formed to overlap with the first electrodeof the display device to form a first capacitor.
 17. The methodaccording to claim 14, further comprising forming a second capacitorelectrode, a second source electrode and a second drain electrode,wherein the second capacitor electrode is connected with one of thesecond source electrode and the second drain electrode.
 18. The methodaccording to claim 17, wherein the second capacitor electrode is formedas one body with the second active layer.
 19. The method according toclaim 1, further comprising forming a third signal line intersectingwith one of the first signal line and the second signal line, whereinthe third signal line is a driving power line.